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10 precautions for Guan Yuda power circuit design

When designing the power adapter circuit, you should pay attention to the following items:

1. Network connectivity, after the schematic design is completed, it is necessary to carefully check the network connectivity to prevent the network from being connected due to writing problems. For example, PWR_IN and PWR-IN may not be obvious in the schematic, but It is a different network.

2. The chip power adapter decoupling problem, when placing the power adapter decoupling capacitor, pay attention to the placement position of the decoupling capacitor. In the digital circuit design, the decoupling capacitor should be placed as close as possible to the IC, and the power adapter should pass through the capacitor first. After reaching the IC, the decoupling capacitors are maximized. In a multi-layer design, the capacitor and IC should be on the same side as much as possible to prevent the capacitor from being connected to the IC through the hole.

3. The digital circuit and the analog circuit are separated as much as possible. When the digital circuit is working, the steep level change will generate a large current. When the internal resistance of the power adapter is relatively large, the power adapter level will fluctuate. In severe cases, It will cause logic level recognition errors, especially the interference effects on analog circuits can not be ignored, so separate the two parts as much as possible.

4. The power adapter loop problem, the loop connecting the power adapter and the ground should be parallel as much as possible to avoid the antenna effect caused by the large circle, which helps to improve the EMC level of the system.

5. Component placement problem, component placement is best with a certain spacing, set the default grid, can make the circuit board design more tidy, the appropriate spacing is also conducive to the board welding and debugging maintenance.

6. Power adapter filter capacitor selection, in the power frequency, you can choose the larger capacity of the electrolytic capacitor, and in the DCDC circuit, according to the power adapter operating frequency, 1M frequency can choose 0.1-10uF chip capacitor, frequency The higher the capacitance is, the smaller the capacitance is. The large capacitance is caused by the presence of the equivalent inductance, and even the oscillation is caused, which exacerbates the ripple of the power adapter.

7. When allowed, the external interface should increase TVS as much as possible to protect the high-voltage and high-voltage serialization caused by other reasons and damage the core circuit.

8. In the prototype debugging phase, increase the LED indication as much as possible, increase the test point as much as possible, and use the test point as much as possible for the GPIO port that is not used, especially for networks that are difficult to pass through the flying line, such as BGA package. Leading the network to increase the resistance or exclusion as much as possible to isolate, can effectively avoid the situation that the circuit can not work due to network error and re-sampled.

9. The power adapter of each function module is preferably separated by the 0R resistor, and a large current can be effectively checked during the commissioning of the power adapter. At the same time, it is possible to monitor the working current of each functional module and timely locate the normal or abnormal operation of the functional module.

10. The circuit design is best designed in layers. Interfaces are used between the modules to facilitate debugging of each functional module.

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